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1 document # sram118 rev c revised august 2006 p4c174 high speed 8k x 8 cache tag static ram features high speed address-to-match - 8 ns maximum access time high-speed read-access time ? 8/10/12/15/20/25 ns (commercial) ? 15/20/25 ns (military) open drain match output reset function 8-bit tag comparison logic automatic powerdown during long cycles data retention at 2v for battery backup operation advanced cmos technology low power operation package styles available ? 28 pin 300 mil dip ? 28 pin 300 mil plastic soj single power supply ? 5v10% functional block diagram pin configuration description the p4c174 is a 65,536 bit high speed cache tag static ram organized as 8k x 8. the cmos memory has equal access and cycle times. inputs are fully ttl-compatible. the cache tag rams operate from a single 5v10% power supply. an 8-bit data comparator with a match output is included for use as an address tag comparator in high speed cache applications. the reset function provides the capability to reset all memory locations to a low level. the match output of the p4c174 reflects the compari- son result between the 8-bit data on the i/o pins and the addressed memory location. 8k cache lines can be mapped into 1m-byte address spaces by comparing 20 address bits organized as 13-line address bits and 7- page address bits. low power operation of the p4c174 is enhanced by automatic powerdown when the memory is deselected or during long cycle times. also, data retention is main- tained down to v cc = 2.0. typical battery backup appli- cations consume only 30 w at v cc = 3.0v. dip (c5, p5), soj (j5)
p4c174 page 2 of 12 document # sram118 rev c maximum ratings (1) symbol parameter value unit v cc power supply pin with ?0.5 to +7 v respect to gnd terminal voltage with ?0.5 to v term respect to gnd v cc +0.5 v (up to 7.0v) t a operating temperature ?55 to +125 c symbol parameter value unit t bias temperature under ?55 to +125 c bias t stg storage temperature ?65 to +150 c p t power dissipation 1.0 w i out dc output current 50 ma recommended operating temperature and supply voltage i sb standby power supply current (ttl input levels) ce v ih com?l. v cc = max ., mil. f = max., outputs open ___ 25 5 ___ ce v hc com?l. v cc = max., f = 0, outputs open mil. v in v lc or v in v hc standby power supply current (cmos input levels) i sb1 grade(2) ambient temperature gnd v cc 0c to +70c symbol c in c out parameter input capacitance output capacitance conditions v in = 0v v out = 0v 5 7 unit pf pf capacitances (4) v cc = 5.0v, t a = 25c, f = 1.0mhz n/a = not applicable symbol dc electrical characteristics over recommended operating temperature and supply voltage (2) v ih v il v hc v lc v cd v ol v oh i li i lo parameter input high voltage input low voltage cmos input high voltage cmos input low voltage input clamp diode voltage output low voltage (ttl load) output high voltage (ttl load) input leakage current output leakage current v cc = min., i in = 18 ma i ol = +8 ma, v cc = min. i oh = ?4 ma, v cc = min. v cc = max. com?l. v in = gnd to v cc mil. v cc = max., ce = v ih , com?l. v out = gnd to v cc mil. min 2.2 ?0.5 (3) v cc ?0.2 ?0.5 (3) 2.4 ?5 ?5 max v cc +0.5 0.8 v cc +0.5 0.2 ?1.2 0.4 +5 +5 notes: 1. stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to maximum rating conditions for extended periods may affect reliability. 2. extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. transient inputs with v il and i il not more negative than ?3.0v and ?100ma, respectively, are permissible for pulse widths up to 20 ns. 4. this parameter is sampled and not 100% tested. typ. 0v 5.0v 10% p4c174 unit v v v v v v v a a ma ma test conditions commercial -10 +10 -10 +10 ___ ___ 40 25 0c to +70c 0v 5.0v 10% commercial
p4c174 page 3 of 12 document # sram118 rev c data retention characteristics (p4c174 military temperature only) symbol v dr i ccdr t cdr t r ? parameter v cc for data retention data retention current chip deselect to data retention time operation recovery time test conditons ce v cc ?0.2v, v in v cc ?0.2v or v in 0.2v min 2.0 0 t rc typ.* v cc = 2.0v 3.0v max v cc = 2.0v 3.0v unit 10 15 600 900 v a ns ns *t a = +251c t rc = read cycle time ? this parameter is guaranteed but not tested. i cc symbol parameter temperature range dynamic operating current* commercial ?8 ?10 ?12 ?15 ?20 ?25 unit ma power dissipation characteristics vs. speed 200 180 170 155 150 *v cc = 5.5v. tested with outputs open. f = max. switching inputs are 0v and 3v. ce = v il , oe = v ih . 170 160 155 ma military data retention waveform
p4c174 page 4 of 12 document # sram118 rev c symbol t rc t aa t oh t ac t lz t hz t oe t olz read cycle time address access time address change to output change chip enable low to output valid chip enable low to output low-z (1) chip enable high to output high -z (1) output enable low to output valid output enable low to output low-z (1) min ?8 unit ns ns ns ns ns ns ns ns ?15 ?20 ?10 ?12 ?25 max min max min max min max min max min max 8 3 3 0 ac characteristics?read cycle (v cc = 5v 10%, all temperature ranges) (2) t ohz output enable high to output high -z (1) t pu chip enable low or address change to powerup t pupd powerup to powerdown note: 1. transition is measured 200 mv from steady state voltage with output load b. 0 8 8 5 5 5 20 10 3 3 0 0 10 10 5 6 5 20 12 3 3 0 0 12 12 5 6 5 20 15 3 3 0 0 15 15 8 8 5 20 20 3 3 0 0 20 20 8 10 8 20 25 3 3 0 0 25 25 10 12 10 25 ns ns ns parameter read cycle no. 1 ( oe oe oe oe oe controlled) (2, 3)
p4c174 page 5 of 12 document # sram118 rev c notes: 1. transition is measured 200 mv from steady state voltage with output load b. this parameter is sampled, not 100% tested. 2. ce is low, oe is low, we is high for read cycle. ce or we must be high during address transitions. 3. all address lines are valid no later than the transition of ce to low. 4. read cycle time is measured from the last valid address to the first transitioning address. 5. powerup occurs as a result of any of the following conditions: a) falling edge of ce . b) falling edge of we ( ce active). c) any address line transition ( ce active). d) any data line transition ( ce and we active). this device automatically powers down after t pupd has elapsed from any of the prior conditions. power dissipation is therefore a function of cycle rate, not ce pulse width. 6. ce is low, we is low for write cycle. ce or we must be high during address transitions. 7. write cycle time is measured from the last valid address to the first transitioning address. 8. oe is low for this write cycle to show t wz and t ow . read cycle no. 2 (address controlled) (2) read cycle no. 3 ( ce ce ce ce ce controlled) (2, 3)
p4c174 page 6 of 12 document # sram118 rev c parameter symbol max max max max max max min min min min min min t wc t cw t as t aw write cycle time chip enable low to end of write address valid to beginning of write address valid to end of write t dw t wp t ah data valid to end of write unit ns ns ns ns ns ns ?25 ?20 ?15 ?12 ?10 ?8 end of write to address change write pulse width end of write to data change t dh write enable high to output low-z (1) t ow write enable low to output high-z (1) t wz 8 7 0 7 0 7 6 0 0 4 10 9 0 9 0 9 6 0 0 4 12 10 0 10 0 10 6 0 0 ac characteristics - write cycle (v cc = 5v 10%, 0c to +70c) 4 15 12 0 12 0 12 7 0 0 5 20 15 0 15 0 15 10 0 0 7 20 15 0 15 0 15 10 0 0 7 ns ns ns ns write cycle no. 1 ( we we we we we controlled) (6) write cycle no. 2 ( ce ce ce ce ce controlled) (6)
p4c174 page 7 of 12 document # sram118 rev c ac characteristics - match cycle (v cc = 5.0v 10%, 0c to +70c) parameter symbol max max max max max max min min min min min min t mc t adm t admh t cem match cycle time address valid to match valid address change to match change chip enable low to match valid t oemhi t cemhi unit ns ns ns ns ns ns ?25 ?20 ?15 ?12 ?10 ?8 chip enable high to match high output enable low to match high 8 3 10 3 12 3 15 3 20 3 25 3 data change to match change t damh data valid to match valid t dam write enable low to match high t wemhi 8 1012152025 788101015 788101015 20 15 12 10 9 7 ns ns ns 7 9 10 12 15 20 7 9 10 13 15 15 000000 match timing
p4c174 page 8 of 12 document # sram118 rev c mode ce ce ce ce ce we we we we we output power standby h x high z standby read l h d out active write l l high z active ac test conditions truth table reset timing ac characteristics - reset cycle (v cc = 5.0v 10%, 0c to +70c) parameter max max max max max max min min min min min min t rrc t rp reset cycle time reset pulse width reset low to powerup unit ns ns ns ns ns ?25 ?20 ?15 ?12 ?10 ?8 35 40 45 50 50 60 t rpu 0 reset low to powerdown t rpd reset low to match high t rmhi reset low to inputs ignored t rix reset low to inputs recognized t rir powerup to reset low t pur 8 35 8 0 0 35 8 10 0 40 10 0 0 40 10 12 0 45 10 0 0 45 12 12 0 50 12 0 0 50 15 15 0 50 15 0 0 50 20 15 0 60 20 0 0 60 25 ns ns ns symbol input pulse levels input rise and fall times input timing reference level output timing reference level output load gnd to 3.0v < 3ns 1.5v 1.5v outputs loads a, b & c
p4c174 page 9 of 12 document # sram118 rev c selection guide the p4c174 is available in the following temperature, speed and package options. ordering information output load a output load b output load c 8 10 12 15 20 25 plastic dip -8pc -10pc -15pc -15pc -20pc -25pc plastic soj -8jc -10jc -15jc -15jc -20jc -25jc miliitary temperature side brazed dip n/a n/a n/a -15cm -20cm -25cm military processed* side brazed dip n/a n/a n/a -15cmb -20cmb -25cmb speed temperature range package commercial * military temperature range with mil-std-883, class b processing. n/a = not available
p4c174 page 10 of 12 document # sram118 rev c side brazed dual in-line package pkg # # pins symbol min max a-0.225 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d-1.485 e 0.240 0.310 ea e l 0.125 0.200 q 0.015 0.070 s1 0.005 - s2 0.005 - c5 28 (300 mil) 0.300 bsc 0.100 bsc pkg # # pins symbol min max a 0.120 0.148 a1 0.078 - b 0.014 0.020 c 0.007 0.011 d 0.700 0.730 e e e1 0.292 0.300 e2 q0.025- j5 28 (300 mil) 0.050 bsc 0.267 bsc 0.335 bsc soj small outline ic package
p4c174 page 11 of 12 document # sram118 rev c pkg # # pins symbol min max a - 0.210 a1 - b 0.014 0.023 b2 0.045 0.070 c 0.008 0.014 d 1.345 1.400 e1 0.270 0.300 e 0.300 0.380 e eb - 0.430 l 0.115 0.150 0 15 0.100 bsc p5 28 (300 mil) plastic dual in-line package
p4c174 page 12 of 12 document # sram118 rev c revisions document number : sram118 document title : p4c174 high speed 8kx8 cache tag static ram rev. issue date orig. of change description of change or 1997 dab new data sheet a oct-05 jdb change logo to pyramid b nov-05 jdb corrected error in selection guide c aug-06 jdb updated soj package information

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